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Low-Temperature Ni-Silicide Initiated Lateral Epitaxial Crystallization with Orientation and Grain Boundary Control for Stackable Transistor Technologies

Authors: Shi, M., Zhang, B., Wang, J., Zhang, J., Li, M.

Journal: 10th IEEE Electron Devices Technology and Manufacturing Conference Emerging Semiconductor Devices and Manufacturing Technologies Edtm 2026

Publication Date: 01/01/2026

DOI: 10.1109/EDTM65772.2026.11496934

Abstract:

A low-temperature silicide initiated lateral epitaxial crystallization (SILEC) technique for 3D transistor stacking is experimentally presented in this work. With barrier modulated phase (BPM) controlled ultrathin NiSi2 as seeds, large size single-crystal-like Si grains up to 4.03 are formed under 600 oC. It's exploited that the orientation consistency and boundary control can be achieved by film thickness constraints asymmetrical seed window design, respectively. As a result, uniform device characteristics are obtained, featuring low sub-threshold swing (~150 mV/dec) and high hole mobility (~40 cm2/V-s).

Source: Scopus